The present disclosure relates to a semiconductor package, a semiconductor device, and a method for manufacturing a semiconductor package.
The performance of electronic devices using semiconductor devices such as semiconductor chips has become higher. It is thus desirable that the density be increased for semiconductor chips that are mounted on a substrate. It is also desirable that substrates including semiconductor chip be smaller is size and occupy less space.
There are various structures for chip-incorporating type semiconductor packages that embed semiconductor chips. For example, a known structure for such a type of a semiconductor package includes a semiconductor chip and a core substrate, which embeds the semiconductor chip. Wiring layers and an external connection terminal, which are formed on an upper surface and a lower surface of the core substrate, are electrically connected to an electrode pad of the semiconductor chip (for example, refer to Japanese Laid-Open Patent Publication Nos. 2006-196785 and 2011-187800). In such a semiconductor package, a through via that extends through the core substrate in a thickness direction electrically connects the wiring layers formed on the upper surface and the lower surface of the core substrate.
A mold resin, for example, is used as the material of a core substrate in a semiconductor package. The mold resin contains a relatively large number of inorganic fillers having large grain diameters. This decreases the coefficient of thermal expansion of the core substrate, and the coefficient of thermal expansion of the core substrate approaches the coefficient of thermal expansion of the semiconductor chip. Thus, warping of the semiconductor package is suppressed. However, when the mold resin is used as the material of the core substrate and a through hole extending through the core substrate in the thickness direction is formed, the large inorganic fillers are exposed from a hole wall surface of the through hole. This forms many ridges and valleys, which may be large, in the hole wall surface thereby making it difficult to form the through via in the through hole. For example, the formation of an electroless plating film may be hindered in a portion of the hole wall surface of the through hole. Otherwise, a large void may form in the through via due to the difference in the plating deposition speed caused by the difference in the surface roughness. An incomplete through via would lower the reliability of the electrical connection between the upper side and the lower side of the core substrate.